Patent details
EP2002542 Title: METHOD AND DEVICE FOR LOW DELAY PROCESSING
Basic Information
- Publication number:
- EP2002542
- PCT Application Number:
- AU2006001778
- Type:
- European Patent Granted for LU
- Legal Status:
- Lapsed
- Application number:
- EP068175355
- PCT Publication Number:
- WO2007095664
- First applicant's nationality:
- Translation Language:
- EPO Publication Language:
- English
- English Title of Invention:
- METHOD AND DEVICE FOR LOW DELAY PROCESSING
- French Title of Invention:
- PROCEDE ET DISPOSITIF POUR LE TRAITEMENT DE FAIBLE RETARD
- German Title of Invention:
- VERFAHREN UND EINRICHTUNG ZUR VERZÖGERUNGSARMEN VERARBEITUNG
- SPC Number:
Dates
- Filing date:
- 23/11/2006
- Grant date:
- 05/01/2022
- EP Publication Date:
- 17/12/2008
- PCT Publication Date:
- 30/08/2007
- Claims Translation Received Date:
- Translations Received Date (B1 EP Publication):
- Translations Received Date (B2 EP Publication):
- Translations Received Date (B3 EP Publication):
- Publication date:
- 05/01/2022
- EP B1 Publication Date:
- 05/01/2022
- EP B2 Publication Date:
- EP B3 Publication Date:
- Lapsed date:
- 23/11/2022
- Expiration date:
- 23/11/2026
- Renunciation date:
- Revocation date:
- Annulment date:
Owner
- From:
- 29/12/2021
- Name:
- Cirrus Logic International Semiconductor Limited
- Address:
- 7B Nightingale Way Quartermile, Edinburgh EH3 9EG, United Kingdom (GB)
Inventor
1
- Name:
- DICKSON, Bonar
- Address:
- Australia (AU)
2
- Name:
- STEELE, Brenton Robert
- Address:
- Australia (AU)
Priority
- Priority Number:
- 2006900854
- Priority Date:
- 21/02/2006
- Priority Country:
- Australia (AU)
Classification
- IPC classification:
- H03H 17/02; G10L 21/0364; H04R 25/00;
Publication
European Patent Bulletin
- Issue number:
- 202201
- Publication date:
- 05/01/2022
- Description:
- Grant (B1)
Annual Fees
- Annual Fee Due Date:
- Annual Fee Number:
- Expected Payer:
- Last Annual Fee Payment Date:
- Last Annual Fee Paid Number:
- Payer:
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