Patent details

EP4075488 Title: METHOD FOR MANUFACTURING SEMICONDUCTOR WAFERS HAVING AN EPITAXIAL LAYER DEPOSITED FROM THE GAS PHASE IN A DEPOSITION CHAMBER

Basic Information

Publication number:
EP4075488
PCT Application Number:
Type:
European Patent Granted for LU
Legal Status:
Lapsed
Application number:
EP211679907
PCT Publication Number:
First applicant's nationality:
Translation Language:
EPO Publication Language:
German
English Title of Invention:
METHOD FOR MANUFACTURING SEMICONDUCTOR WAFERS HAVING AN EPITAXIAL LAYER DEPOSITED FROM THE GAS PHASE IN A DEPOSITION CHAMBER
French Title of Invention:
PROCÉDÉ DE FABRICATION DE PLAQUETTES SEMI-CONDUCTRICES À COUCHE ÉPITAXIALE DÉPOSÉE EN PHASE GAZEUSE DANS UNE CHAMBRE DE DÉPÔT
German Title of Invention:
VERFAHREN ZUM HERSTELLEN VON HALBLEITERSCHEIBEN MIT AUS DER GASPHASE ABGESCHIEDENER EPITAKTISCHER SCHICHT IN EINER ABSCHEIDEKAMMER
SPC Number:

Dates

Filing date:
13/04/2021
Grant date:
28/02/2024
EP Publication Date:
19/10/2022
PCT Publication Date:
Claims Translation Received Date:
Translations Received Date (B1 EP Publication):
Translations Received Date (B2 EP Publication):
Translations Received Date (B3 EP Publication):
Publication date:
28/02/2024
EP B1 Publication Date:
28/02/2024
EP B2 Publication Date:
EP B3 Publication Date:
Lapsed date:
13/04/2024
Expiration date:
13/04/2041
Renunciation date:
Revocation date:
Annulment date:

Owner

From:
21/02/2024
 
 

Name:
Siltronic AG
Address:
Einsteinstraße 172 Tower B / Blue Tower, 81677 München, Germany (DE)

Inventor

Name:
Stettner, Thomas
Address:
Germany (DE)

Classification

IPC classification:
H01L 21/68;

Publication

European Patent Bulletin

Issue number:
202409
Publication date:
28/02/2024
Description:
Grant (B1)

Annual Fees

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Expected Payer:
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